Every electronic device, from a phone to an AI server, is built from chips. Making the chips is only half the job. They also have to be connected to each other and to the rest of the device, and that step is called packaging.
For decades, progress came from shrinking the transistor, the tiny switch inside a chip. That route is slowing down. A growing share of today’s gains in speed, power efficiency and density now comes from a different question: how well are chips connected once they exist?
Hybrid bonding is one answer. Instead of joining chips with tiny balls of solder, it fuses copper pads and the insulating layer around them directly together. The result is many more connections in the same space, with shorter paths between chips. That matters most for AI processors and memory.
At IeB, we see hybrid bonding as more than a packaging option. It is becoming a contest for control of the connection between chips, played out across equipment, materials, intellectual property and manufacturing know how. This article explains how the technology works, where the market stands, who is shaping it and how IeB can support companies how to respond.
What Is Hybrid Bonding and How Does It Work?
Hybrid bonding joins two chips, or two wafers, by pressing their surfaces together until they fuse into one solid piece. It is called hybrid because it forms two kinds of bond at the same time. The insulating layer (the dielectric, usually silicon oxide) bonds to the insulating layer, and copper bonds to copper. The copper pads carry the electrical signals, and the oxide holds everything together. There is no solder in between, and the two surfaces meet face to face.
The three panels above show how the bond forms, from left to right:
- Oxide meets oxide. The two oxide surfaces touch and bond at room temperature.
- Heat closes a tiny gap. Copper expands more than oxide does when heated, so the copper pads grow slightly and close the small gap left above them (the dishing gap).
- More heat joins the copper. Further heating presses the copper pads against each other without any outside pressure.
What remains is one continuous bonded surface that carries signals directly from one chip to the next. Because the connections are so small and so close together, hybrid bonding is classed as an advanced packaging technology, and it goes further in that direction than any other approach in production today.
Types of Hybrid Bonding: W2W, D2W and D2D
There are three types of hybrid bonding, and the difference is simply what is being joined. All three bond copper to copper and dielectric to dielectric at the same time. Think of a wafer as a full sheet of stamps, and each die as one stamp on that sheet.
| Type | What is joined | Plain language |
|---|---|---|
| Wafer to wafer (W2W) | Two whole wafers | Two full sheets are bonded together. This is where the technology first reached the market. |
| Die to wafer (D2W) | One die onto a wafer | Individual stamps are placed onto a full sheet. It suits designs that combine dies of different sizes or origins. |
| Die to die (D2D) | Two single dies | Two individual stamps are bonded directly to each other. |
Hybrid Bonding Materials: Silicon Oxide vs Polymer
Hybrid bonding pairs metal with one of two insulating materials, silicon oxide or a polymer (a plastic like material). Each choice changes how the bond behaves, how forgiving the process is, and which equipment is needed.
| What to compare | Silicon oxide with metal | Polymer with metal |
|---|---|---|
| Bonding temperature | Room temperature | Lower temperature |
| Behavior during bonding | No reflow or deformation, so the surface keeps its shape | The polymer reflows, meaning it softens and flows |
| Stiffness (modulus) | High, so it absorbs stress poorly | Lower |
| Sensitivity to particles | High, because tiny particles can cause defects | Lower, so it tolerates particles better |
| Main strength | A stable bond that does not deform | A more forgiving process when surfaces are less clean |
| Main trade off | Demands a very clean process | The material flows during bonding and is less stiff |
In short, silicon oxide gives a stable bond but needs very clean conditions, while polymer forgives particles but flows during bonding. That trade between process cleanliness and mechanical behavior shapes equipment and materials choices throughout the supply chain.
Key Benefits of Hybrid Bonding
Removing the solder bump changes what a package can do. IeB’s technical assessment lists these benefits, explained here in plain terms:
- 3D stacking and direct connections: Chips can be stacked vertically and wired together directly. This is the foundation for chiplet and memory designs.
- The highest I/O of any packaging approach: More connections fit into each square millimeter than with any bump based method.
- Bonding pitch below 10 microns: The connections are spaced closer than micro bumps can manage.
- Higher memory density: More memory fits in the same footprint as stacks grow taller.
- Expanded bandwidth: Many short connections move more data between chips at once.
- Better power efficiency and speed: Signals travel shorter distances, so less energy is spent per bit and transfers are faster.
- No bump penalties: Removing bumps improves performance without adding power or signal losses.
- Smaller connections and smaller packages: Both the interconnect pitch and the overall structure shrink.
From Solder Balls to Hybrid Bonding: The Interconnect Pitch Evolution
Pitch is the spacing between neighboring connections, and packaging has moved steadily toward smaller pitches. Each step down opened the door to a new class of product. Hybrid bonding is the largest step so far.
| Stage | Pitch | Feature size | Material |
|---|---|---|---|
| Solder balls for PCB assembly | 300 to 500 microns | Ball 150 to 300 microns | BGA solder balls |
| Fine pitch bumping | 50 to 100 microns | Bump 25 to 50 microns | Solder bumps, pillar bumps with solder cap |
| Solder micro bump bonding | 20 to 50 microns | Bump 12 to 25 microns | Solder bumps, pillar bumps with solder cap |
| Hybrid bonding | 10 microns to under 2 microns | Pad 1 to 6 microns | Planarized copper pads, copper and silicon oxide |
For scale, a human hair is roughly 70 microns wide. The first stage above is several hair widths apart, while hybrid bonding connections can sit a fraction of a hair width apart.
What this means for connection density.
I/O density means how many connections fit in one square millimeter. The chart below plots it against pitch. Moving right means a finer pitch, and moving up means more connections.
- Flip chip with micro bumps and Cu pillars delivers roughly 100 to 300 I/Os per square millimeter, and embedded silicon bridges sit in a similar band.
- Fan-out, 2.5D silicon interposers, and flip-chip with standard bumps all sit lower.
- Hybrid bonding, the bump-less approach, stands alone above 10,000 I/Os per square millimeter at a pitch under 5 microns.
That gap is a change of category, not a small improvement. Category changes tend to reorder where value sits in a supply chain, and whoever masters the connection between chips controls a growing share of what the finished product can do.
How Hybrid Bonding Compares with Other Advanced Packaging Technologies
The figure below compares common packaging methods by architecture and substrate, showing where hybrid bonding fits among traditional, advanced, and emerging approaches.
Each column is a packaging architecture, meaning how the chips are connected. Each row is a substrate, meaning the base the chip sits on before it reaches the circuit board (PCB). The rows are organic IC substrate, no substrate, ceramic substrate and lead frame substrate. The columns run from traditional packaging on the left to emerging formats on the right.
| Column | What it means in plain language | Examples on the slide |
|---|---|---|
| Wire bond (traditional) | The chip is connected to its base with thin metal wires. | WB CSP, WB BGA, BOC, COB, LTCC and HTCC, DIP, SOT and TSOP, QFN |
| Flipped die (advanced) | The chip is turned upside down so its connections face the base, and it connects through solder bumps. | FC BGA, FC CSP, FC SiP, Fan Out, Fan In, FC QFN |
| Embedded die (advanced) | The chip sits inside the substrate instead of on top of it. | Embedded silicon bridge, embedded die and passives, FOPLP |
| 2.5D (advanced) | Chips sit side by side on a thin silicon layer called an interposer. | Silicon interposers |
| 3D (advanced) | Chips are stacked on top of each other. TSV stands for through silicon via, a tiny vertical channel that carries signals through a chip. | 3DS TSV for stacked DRAM, HBM TSV, NAND TSV, copper to copper hybrid bonding (WoW) |
| Emerging (advanced) | Newer formats that are still moving into the market. | Hybrid bonding SoC on interposer, hybrid bonding SoC in fan out, embedded multi die and passives |
Where Does Hybrid Bonding Appear?
It shows up in two places, both on the right side of the grid.
- In the 3D column, as copper to copper hybrid bonding for wafer to wafer (WoW). Two wafers are joined face to face directly through their copper pads, with no solder bumps or wires between them. Right next to it, the slide lists TSV based stacking for DRAM, HBM and NAND, which is the approach hybrid bonding competes with.
- In the emerging column, as SoC on interposer and SoC in fan out. An SoC (system on chip) is a single chip that holds the functions of a whole system. Both formats are shown with TSMC as the source.
The emerging column also lists embedded multi die and passives formats, sourced to JCET. The slide does not label those as hybrid bonding.
The takeaway is that hybrid bonding is the newest option on the grid. TSMC, Intel and AMD already use it in their products, so it has clearly moved beyond the laboratory.
Why Demand for Hybrid Bonding Is Accelerating?
Four pressures are pushing the industry toward hybrid bonding. IeB’s market outlook summarizes them in the panel below.
- AI workloads need to move a lot of data using little energy. Chips that run AI are limited by how fast data can travel, and by the power it takes. Many short vertical connections and lower energy per bit help directly.
- Micro bumps are reaching their limits. Once HBM memory stacks exceed 12 layers, pitch, resistance to heat flow and reliability all become harder to manage with conventional connections.
- Advanced logic chips need direct die to die links. Conventional 2.5D methods struggle to meet the latency (delay), power and size goals of the newest designs.
- Data centers are already buying. IeB’s market analysis notes that data centers are deploying chipsets designed with die to wafer hybrid bonding, with installations reported to be rising about 40% year on year.
IeB analysts also expect the technology to gain traction in high performance computing (HPC), AI chiplets and autonomous driving, because its smaller connection pitch outperforms other packaging technologies. For technology leaders, hybrid bonding is moving from a roadmap item to a planning assumption for the next generation of AI and memory products.
Hybrid Bonding Market Size and Forecast
Companies buy the machines that do the bonding before they ship products in volume, so the market for these tools is a useful early signal. The figures below come from Dataintelo’s analysis, combined with IeB assumptions. They cover the tool market specifically, not the revenue of hybrid bonded packaging as a whole.
Market size and growth
- 2025: about $1.8 billion
- 2034 forecast: $6.2 billion
- Growth rate: a compound annual growth rate (CAGR) of 14.7% over 2026 to 2034. CAGR is the steady yearly growth rate that would take the market from its starting size to its end size.
The market was roughly $0.6 billion in 2019, $0.9 billion in 2021 and $1.4 billion in 2023. Projections put it at $2.1 billion in 2026, $2.7 billion in 2028 and $4.2 billion in 2031. That is more than a threefold rise between 2025 and 2034.
Which Hybrid Bonding Tools Leads: Die to Wafer or Wafer to Wafer?
- Die to wafer tools lead with 52.4% of the market.
- Wafer to wafer tools follow with 39.8%.
- Other types make up 7.8%.
Die to wafer’s lead fits the move toward chiplets and memory stacking, where dies of different sizes and origins have to be combined.
Where Hybrid Bonding Demand Sits: Regions
- Asia Pacific: 48.3%
- North America: 24.6%
- Europe: 14.2%
- Middle East and Africa: 7.1%
- Latin America: 5.8%
With nearly half of demand in one region, supply planning, partnerships and market entry decisions all carry a strong regional dimension.
Hybrid Bonding in Products: Sony, TSMC and Intel
The easiest way to see what hybrid bonding does is to look at where it is already used. The three examples below run from a camera sensor to the processors inside AI data centers.
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Sony: the first hybrid bonded product
The first commercial hybrid bonding product was a Sony CMOS image sensor (CIS), the light sensing chip in a camera. It was built with wafer to wafer bonding, which joins the pixel layer to the image signal processor (ISP), the chip that turns the raw light signal into a usable image. The cross section below shows the copper to copper and oxide to oxide bonds at the joint.
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TSMC 3DFabric
TSMC, a major contract chip manufacturer, delivers hybrid bonding through its 3DFabric platform. The platform combines fine pitch chip to chip connections with wafer level processing, and it has two families.
| Family | What it covers | Variants |
|---|---|---|
| Front end chip stacking (FE 3D) | SoIC, which reassembles chiplets that were split out of a system on chip (SoC). It supports both chip on wafer and wafer on wafer schemes. | CoW (chip on wafer), WoW (wafer on wafer) |
| Back end advanced packaging (BE 3D) | InFO, a chip first approach, and CoWoS, a chip last approach. Chip first means the chips are placed before the wiring layers are built, and chip last means the wiring is built first. | InFO R (RDL interconnect), InFO L (LSI plus RDL interconnect), CoWoS S (silicon interposer), CoWoS R (RDL interposer), CoWoS L (LSI plus RDL interposer) |
SoIC chips can be assembled in conventional packages, combined with the back end services above, or paired with TSMC SoW, and they target HPC, AI and mobile applications. TSMC’s own chart of density against bonding pitch shows the progression from 2.5D with micro bumps, to 3D IC, to the SoIC bond as the densest option.
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Intel Foveros Direct 3D
Intel reaches a similar point by a different route. Foveros Direct 3D drops solder micro bumps from die to die connections and uses direct copper to copper bonding to stack chiplets on an active base die, meaning a base chip that carries circuits of its own.
Key figures from Intel’s materials:
- Pitch below 10 microns.
- More than 10,000 connections per square millimeter.
- Energy below 0.05 picojoules per bit, where a picojoule is the tiny unit of energy used to move one bit of data.
- Up to 10 times finer interconnect density than conventional micro bump technologies.
- 16 times the bump density of Foveros at 36 micron pitch, with higher bandwidth at lower latency, power and die area.
- Used in Intel Foundry products since 2025.
Intel’s packaging ladder shows how large the jump is. Each step down the table raises connection density and cuts the energy needed per bit.
| Technology | Pitch | Density per mm² | Energy per bit |
|---|---|---|---|
| Standard package | About 100 microns | About 100 | 1.7 pJ |
| EMIB | 45 to 55 microns | 330 to 772 | 0.50 pJ |
| Foveros | 25 to 50 microns | 400 to 1,600 | 0.15 pJ |
| Foveros Omni | 25 microns | About 1,600 | Below 0.15 pJ |
| Foveros Direct | Below 10 microns | Above 10,000 | Below 0.05 pJ |
Intel Foundry groups these under its systems of chips portfolio: FCBGA 2D and 2D+, EMIB 2.5D and 3.5D, Foveros 2.5D and Foveros Direct 3D. AMD is also among the companies adopting hybrid bonding.
Taken together, TSMC and Intel show that hybrid bonding has moved from a niche in imaging to the core of flagship HPC and AI platforms.
Hybrid Bonding Challenges: Yield, Alignment and Cleanliness
Hybrid bonding rewards those who can manufacture it, and it is unforgiving. The surfaces being joined are so small and so flat that tiny errors become failures. IeB’s market outlook lists the main challenges.
- Alignment precision: Chips must be placed with an accuracy below 50 nanometers (a nanometer is a billionth of a meter), or the connections fail.
- Cleanliness and surface roughness: Surfaces must be atomically clean, with roughness under 0.5 nm RMS. Particles, voids and wafer warpage all turn into defects.
- Yield: IeB’s market analysis puts the average yield of hybrid bonded dies at about 85% in 2023, against roughly 96% for conventional bump based connections. In practice, that means about 85 working parts out of every 100, compared with about 96.
- Throughput: Production speed has to keep pace with cost targets.
- Everything around the process: There are no industry wide standards, trained workers are scarce, and the supply chain around bond interface metrology (the measurement of the bond) is complex.
Closing the yield gap is the central industrial challenge. The steps where it can be closed are surface preparation, CMP (chemical mechanical polishing, which flattens surfaces), plasma activation, cleaning, alignment, bonding, annealing (a heat treatment), inspection and metrology.
These constraints also create room for new players. Equipment makers that improve alignment and throughput, materials suppliers that deliver cleaner and more particle tolerant surfaces, and metrology specialists that can see defects at the bond interface all stand to gain from a yield gap the industry wants to close.
Hybrid Bonding Patents: Who Holds the IP
A patent gives its owner the right to stop others from using an invention without permission. That is why it matters who holds the patents on hybrid bonding: a company that wants to build or sell hybrid bonded products may need a license. Knowmade’s analysis tracks patent publication years from 2015 to 2023 and shows the IP arriving in three waves.
- Early innovators: Adeia, TSMC and Intel.
- Players with steadily rising IP activity: TSMC, Intel, Micron, Adeia, XMC, Samsung and YMTC.
- Newcomers, with first hybrid bonding patents published in 2020 or later: memory makers CXMT, Sunrise Memory and SK hynix; OSATs ASE, SJSemi and Tongfu Microelectronics; and equipment and materials suppliers Saultech, Applied Materials, HD MicroSystems and Resonac.
Adeia’s position traces back to the DBI technology from Ziptronix, acquired in 2015, and the company has turned that early lead into a licensing business. Its licensees include Sony, OmniVision, SK hynix, Tower Semiconductor, Canon, SkyWater, YMTC, Micron, LAPIS, Kioxia, Western Digital, etc.
Ownership of hybrid bonding IP is spreading well beyond the original pioneers. For any company entering or scaling in this space, freedom to operate, licensing exposure and patent positioning belong in the business case from the start.
The Hybrid Bonding Value Chain and Recent Deals
No single company delivers hybrid bonding. IeB’s value chain analysis groups the ecosystem into seven roles:
| Role | What they do | Examples |
|---|---|---|
| Foundries | Implement the technology in manufacturing | TSMC, Intel, UMC, Samsung Electronics, Tower Semiconductor, GlobalFoundries |
| Fabless companies | Design chips, including 3D chiplet architectures, but do not own factories | AMD, Qualcomm, Xilinx, OmniVision, NVIDIA, Graphcore |
| Equipment providers | Supply bonding, inspection and process tools | Applied Materials, TEL, KLA, Besi, EVG, Lam Research, SET, Saultech, ASMPT, Canon |
| IP providers | License and develop core know how | Adeia, CEA Leti, imec, Fraunhofer, ASTAR |
| IDMs and end device makers | Bring the technology into finished products. An IDM (integrated device manufacturer) both designs and makes its own chips | Sony, Intel, Samsung, Kioxia, SK hynix, CXMT, OmniVision, Nanya, Sunrise Memory |
| Material providers | Supply the dielectrics and chemistries | HD MicroSystems, DuPont, Resonac, Entegris, Shin Etsu, Brewer Science |
| Government institutes | Conduct research on hybrid bonding | CEA Leti, imec, Sandia National Laboratories, ITRI |
Hybrid Bonding: Key Recent Activities
- Applied Materials and Besi (2025): To accelerate the use of hybrid bonding in advanced logic and memory chips, Applied Materials, in collaboration with BE Semiconductor Industries N.V. (Besi), developed the Kinex™ Bonding system – the industry’s first integrated die-to-wafer hybrid bonder. The system brings together Applied’s expertise in front-end wafer and chip processing with high levels of bonding accuracy and speed from Besi’s leading die placement, interconnect and assembly solutions. Applied also bought a 9% stake in Besi, a leading manufacturer of assembly equipment for the semiconductor industry.
- QCi and NHanced (June 2026): QCi acquired NHanced in June in a transaction initially valued at $73.1 million in cash and stock. NHanced brings advanced semiconductor packaging and manufacturing capabilities, including hybrid bonding, chiplet architectures and photonic-device integration. QCi said the acquisition allowed it to launch its planned Fab 2 manufacturing initiative ahead of schedule.
- Adeia and UMC (2026): Adeia Inc. announced that it has expanded and renewed its intellectual property (IP) licensing relationship with United Microelectronics Corporation (UMC). The new agreement provides UMC with continued access to Adeia’s semiconductor portfolio, including hybrid bonding technologies, and extends the companies’ collaboration into future generations of 3D integration and advanced packaging solutions.
- ChangXin Memory Technologies: Chinese memory giant Yangtze Memory Technologies Corp. (YMTC) announced a partnership with ChangXin Memory Technologies (CXMT) to boost HBM production using YMTC’s proprietary Xtacking hybrid bonding technology.
- Saultech: The company announced a die bonder machine DB-22H Ultra for advance C2W-WLP (Chip to Wafer-Wafer Level Packaging) processes.
- Resonac and US JOINT: Resonac unveiled a new consortium of ten partners, called “US-JOINT,” for its semiconductor back-end process R&D in Silicon Valley. The ten American and Japanese semiconductor materials and equipment companies are: Azimuth; KLA; Kulicke & Soffa; Moses Lake Industries; MEC; ULVAC; NAMICS; TOK; TOWA; and Resonac.
The pattern is the same across all of these moves. Companies are assembling complete solutions, because the value depends on how well the pieces work together.
How IeB Can Help With Hybrid Bonding Research
As hybrid bonding advances across semiconductor manufacturing, companies need to evaluate not only its technical potential but also its commercial viability, competitive landscape and intellectual property implications. The industry is moving toward higher density, heterogeneous and 3D integration, where conventional solder based interconnects face limits in pitch, power efficiency, thermal performance and scaling. Hybrid bonding is emerging as a key enabler for chiplet integration, 3D stacking, advanced memory, logic and high performance computing.
Ingenious e-Brain (IeB) tracks hybrid bonding for advanced packaging and 3D integration, covering technology advances, ecosystem development, adoption timelines, competitive positioning and emerging applications. Our coverage spans the full value chain, from materials and equipment providers, foundries, fabless companies, IP providers and IDMs to government institutes and end users. Our team evaluates emerging semiconductor technologies from both technology and business perspectives, including the competitive landscape, cost dynamics, process scalability, supply chain readiness, IP positioning and adoption potential. The table below shows where our support fits.
| If you need to know | IeB support | What you get |
|---|---|---|
| Which technologies, equipment and partners to watch |
Technology scouting & monitoring and Technology forecasting |
A clear view of developments in wafer to wafer, die to wafer and die to die bonding, plus the materials, tools and competing packaging options around them, so R&D priorities rest on evidence. |
| How big the opportunity is and who is winning it |
Market intelligence through Business Consulting and competitive intelligence |
Market size, growth drivers, regional trends, adoption barriers and a benchmark of key players across the value chain. |
| Who owns the IP and where the risks are |
Patent analytics, patent landscape analysis and freedom to operate search |
Patent landscapes across processes, equipment and materials, competitor portfolios, white spaces and an assessment of infringement risk before you commit. |
| Whether a technology or a target is worth backing |
Technology due diligence and technology audit and advisory |
An assessment of maturity, scalability, manufacturing constraints and commercial potential to support investments, partnerships and acquisitions. |
By combining technical research, market analysis and IP expertise, IeB helps organizations understand where hybrid bonding could create value and how to position themselves in the evolving semiconductor packaging ecosystem.
A dedicated hybrid bonding study from IeB can cover:
- Technology maturity: The current state of hybrid bonding and how it compares with wire bonding, flip chip, micro bumps and Cu pillars, 2.5D interposers and TSV based 3D integration.
- Key players: Academic groups, start ups, equipment makers, materials suppliers, foundries, IDMs and technology developers, with their latest developments and strategies.
- Competitive positioning: The technology roadmaps, partnerships, investments and commercialization strategies of industry leaders.
- Critical technology challenges: Surface preparation of wafers and dies, alignment accuracy, surface roughness, cleanliness, bonding temperature, defects, void formation, yield, wafer warpage and process throughput.
- Process and equipment bottlenecks: The steps that limit dielectric to dielectric and metal to metal bonding, across CMP, plasma activation, cleaning, alignment, bonding, annealing, inspection and metrology.
- Applications and adoption timelines: Opportunities across 3D NAND, HBM, advanced logic, chiplets, image sensors, RF, AI and HPC, and other emerging uses.
- Risks to weigh before investing: Research gaps, technical risks, manufacturing challenges and scalability concerns.
- Future requirements: The technology and material needs that will shape the ecosystem, and the openings for new materials, equipment, process technologies and enabling solutions.
Conclusion: Hybrid Bonding Is Now a Strategy Question
Hybrid bonding began as a way to make image sensors smaller. It is now a core part of how AI processors and high bandwidth memory are built. The technology brings a finer pitch, denser connections and lower energy per bit. It also brings hard problems in alignment, cleanliness and yield, and a patent landscape that is becoming more crowded.
For companies in this space, the decision is no longer whether hybrid bonding matters. The decision is where to invest, whom to partner with and which IP risks to manage. The companies that answer those questions early are best placed as adoption grows.
Explore how IeB can support your hybrid bonding strategy. Connect with our technology experts and business consultants for tailored research and consulting across technology scouting, market intelligence, technology due diligence and IP analysis.
Contact us at contact@iebrain.com or fill out the form to discuss your requirements.
